View L6728ATR_4964542.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

L6728A
High frequency single phase PWM controller with Power Good
Features

Flexible power supply from 5 V to 12 V Power conversion input as low as 1.5 V 0.8 V internal reference 0.8 % output voltage accuracy High-current integrated drivers Power Good output Sensorless and programmable OCP across low-side RDS(on) OV / UV protections VSEN disconnection protection Oscillator internally fixed at 600 kHz LS-LESS to manage pre-bias start-up Adjustable output voltage Disable function Internal soft-start VFDFPN 10 package VFQFPN 10
Description
L6728A is a single-phase step-down controller with integrated high-current drivers that provides complete control logic and protection to realize in a simple way general DC-DC converters by using a compact VFDFPN 10 package. Device flexibility allows managing conversions with power input VIN as low as 1.5 V and device supply voltage ranging from 5 V to 12 V. L6728A provides simple control loop with voltage mode EA. The integrated 0.8 V reference allows regulating output voltages with 0.8 % accuracy over line and temperature variations. Oscillator is internally fixed to 600 kHz. L6728A provides programmable dual level over current protection as well as over and under voltage protection. Current information is monitored across the low-side MOSFET RDS(on) saving the use of expensive and spaceconsuming sense resistors. PGOOD output easily provides real-time information on output voltage status, through VSEN dedicated output monitor.
Applications

Memory and termination supply Subsystem power supply (MCH, IOCH, PCI) CPU and DSP power supply Distributed power supply General DC / DC converters
Table 1.
Device summary
Order codes L6728A L6728ATR Package Packing Tube Tape and reel
VFDFPN 10 VFDFPN 10
October 2008
Rev 1
1/32
www.st.com 1
L6728A
Contents
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1 Over-current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 9
Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 13 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9.1 9.2 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 10.2 10.3 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/32
L6728A
Contents
11
20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.1 Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1.1 11.1.2 11.1.3 11.1.4 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Signal input (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.2
Demonstration board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12
5A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12.1 Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1.1 12.1.2 12.1.3 12.1.4 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Signal input (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.2
Demonstration board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13 14
Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
L6728A
Typical application circuit and block diagram
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VIN = 1.5V to 12V VCC = 5V to 12V CDEC RPG PGOOD 10 PGOOD 6 VCC BOOT 1 CHF HS L Vout CBULK
L6728A
7
COMP / DIS
UGATE
3
CF CP RF 8
PHASE
2
FB VSEN 9
LGATE / OC GND 5
4
LS
COUT
LOAD
ROS
RFB
ROCSET
ROS
L6728A Reference Schematic
RFB
1.2
Block diagram
Figure 2. Block diagram
VCC
VOUT MONITOR CONTROL LOGIC & PROTECTIONS
VSEN
OC
VOCTH
PGOOD
BOOT
ADAPTIVE ANTI CROSS CONDUCTION
CLOCK
HS
UGATE PHASE
PWM 600 kHz OSCILLATOR ERROR AMPLIFIER + -
VCC
LS
LGATE / OC GND
L6728A
COMP / DIS FB
0.8V IOCSET
4/32
L6728A
Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 3. Pins connection (top view)
BOOT PHASE UGATE LGATE / OC GND
1 2 3 4 5
10 9
L6728A
8 7 6
PGOOD VSEN FB COMP / DIS VCC
2.1
Pin descriptions
Table 2.
Pin #
Pin description
Name Function HS driver supply. Connect through a capacitor (100 nF) to the floating node (LS-Drain) pin and provide necessary bootstrap diode from VCC. HS driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RDS(on) drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS MOSFET is OFF. HS driver output. Connect directly to HS MOSFET gate.
1
BOOT
2
PHASE
3
UGATE
4
LGATE. LS driver output. Connect directly to LS MOSFET gate. OC over-current threshold set. During a short period of time following VCC rising over UVLO threshold, a 10 A current is sourced from this pin. Connect to GND with an ROCSET resistor greater than 5 k to program OC LGATE / OC Threshold. The resulting voltage at this pin is sampled and held internally as the OC set point. Maximum programmable OC threshold is 0.55 V. A voltage greater than 0.6 V activates an internal clamp and causes OC threshold to be set at the maximum value. GND VCC All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. Device and Drivers power supply. Operative range from 5 V to 12 V. Filter with at least 1 F MLCC to GND.
5 6
7
COMP. Error amplifier output. Connect with an RF - CF // CP to FB to compensate the device control loop. COMP / DIS DIS. The device can be disabled by pushing this pin lower than 0.75 V (typ). Setting free the pin, the device enables again. FB Error amplifier inverting input. Connect with a resistor RFB to the output regulated voltage. Output resistor divider may be used to regulate voltages higher than the reference.
8
5/32
L6728A Table 2.
Pin # 9
Pins description and connection diagrams Pin description (continued)
Name VSEN Function Regulated voltage sense pin for OVP and UVP protections and PGOOD. Connect to the output regulated voltage, or to the output resistor divider if the regulated voltage is higher than the reference. Open drain output set free after SS has finished and pulled low when VSEN is outside the relative window. Pull up to a voltage equal or lower than VCC. If not used it can be left floating.
10
PGOOD
2.2
Thermal data
Table 3.
Symbol RTH(JA) RTH(JC) TMAX TSTG TJ PTOT
Thermal data
Parameter Thermal resistance junction to ambient (Device soldered on 2s2p, 67 mm x 69 mm board) Thermal resistance junction to case Maximum junction temperature Storage temperature range Junction temperature range Maximum power dissipation at TA = 25 C Value 45 5 150 -40 to 150 -40 to 125 2.25 Unit C/W C/W C C C W
6/32
L6728A
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol VCC VBOOT, VUGATE to GND to PHASE to GND to GND; t < 200 ns to GND to GND; t < 200 ns to GND FB, COMP, VSEN to GND PGOOD to GND
Absolute maximum ratings
Parameter Value -0.3 to 15 15 33 45 -5 to 18 -8 to 30 -0.3 to VCC+0.3 -0.3 to 3.6 -0.3 to VCC+0.3 Unit V
V
VPHASE VLGATE
V V V V
3.2
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VCC = 5 V to 12 V; TJ = 0 C to 70 C unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-on ICC IBOOT UVLO Oscillator FSW VOSC dMAX Main oscillator accuracy PWM ramp amplitude Maximum duty cycle 67 540 600 1.4 660 kHz V % VCC supply current BOOT supply current VCC turn-ON Hysteresis UGATE and LGATE = OPEN UGATE = OPEN; PHASE to GND VCC rising 0.2 6 0.7 4.1 mA mA V V
Reference and error amplifier Output voltage accuracy A0 GBWP SR DIS DC gain
(1) (1)
-0.8
120 15 8
0.8
% dB MHz V/s
Gain-bandwidth product Slew-rate (1) Disable threshold
COMP falling
0.70
0.85
V
7/32
L6728A Table 5.
Symbol Gate drivers IUGATE RUGATE ILGATE RLGATE HS source current HS sink resistance LS source current LS sink resistance BOOT - PHASE = 5 V BOOT - PHASE = 5 V VCC = 5 V VCC = 5 V
Electrical specifications Electrical characteristics (continued) (VCC = 5 V to 12 V; TJ = 0 C to 70 C unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit
1.5 1.1 1.5 0.65
A A
Over-current protection IOCSET VOC_SW OCSET current source OC switch-over threshold Sourced from LGATE pin, during OC setting phase VLGATE/OC rising 9 10 600 11 A mV
Over and under-voltage protections VSEN rising OVP UVP VSEN PGOOD Upper threshold PGOOD Lower threshold VPGOODL PGOOD voltage low VSEN falling IPGOOD = -4 mA 0.680 0.710 0.740 0.4 V V VSEN rising 0.860 0.890 0.920 V OVP threshold unlatch, VSEN Falling UVP threshold VSEN bias current VSEN falling Sourced from VSEN 0.35 0.50 0.40 0.60 100 0.45 0.70 V V nA 0.90 1.00 1.10 V
1. Guaranteed by design, not subject to test.
8/32
L6728A
Device description
4
Device description
L6728A is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 10-pin device allows reducing cost and size of the power supply solution also providing real-time PGOOD in a compact VFQFPN10 3x3 mm. L6728A is designed to operate from a 5 V or 12 V supply. The output voltage can be precisely regulated to as low as 0.8 V with 1 % accuracy over line and temperature variations. The switching frequency is internally set to 600 kHz. This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8 V/s slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, L6728A provides over-current protection as well as overvoltage, under voltage and feedback disconnection protection. The over-current trip threshold is programmable by a simple resistor connected from Lgate to GND. Output current is monitored across low-side MOSFET RDS(on), saving the use of expensive and spaceconsuming sense resistor. Output voltage is monitored through dedicated VSEN pin. L6728A implements soft-start increasing the internal reference in closed loop regulation. low-side-less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side. L6728A is available in a compact VFDFN10 3 x 3 mm package with exposed pad.
9/32
L6728A
Driver section
5
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode: to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied; to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely.
5.1
Power dissipation
L6728A embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Device bias power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
P DC = V CC ( I CC + I BOOT )
Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results:
P SW = F SW ( Q gHS V BOOT + Q gLS V CC )
External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device.
10/32
L6728A
Soft-start
6
Soft-start
L6728A implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. The device gradually increases the internal reference from 0 V to 0.8 V in 4.5 msec (typ.), in closed loop regulation, linearly charging the output capacitors to the final regulation voltage. A pre-charged output voltage will affect the soft-start duration, resulting in a reduction of this period of time (< 4 msec). During the soft-start process all the protections but the UVP are active: the UVP becomes active as soon as the soft-start ends up. The device begins soft-start phase only when VCC power supply is above UVLO threshold and over-current threshold setting phase has been completed.
6.1
Low-side-less start up (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during start-up, L6728A performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. If the output voltage is pre-biased to a voltage higher than the final one, the HS would never start to switch. In this case, at the end of soft-start time, LS is enabled and discharge the output to the final regulation value. This particular feature of the device masks the LS turn-on only from the control loop point of view: protections by-pass this turning ON the LS MOSFET in case of need. Figure 4. LSLess startup (left) vs. non-LSLess startup (right)
11/32
L6728A
Over-current protection
7
Over-current protection
The over-current function protects the converter from a shorted output or overload, by sensing the output current information across the low side MOSFET drain-source onresistance, RDS(on). This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RDS(on) current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP thresholds voltages, internally held. If the monitored voltage is bigger than these thresholds, an over-current event is detected. For maximum safety and load protection, L6728A implements a dual level over-current protection system:
1st level threshold: it is the user externally set threshold. If the monitored voltage on PHASE exceeds this threshold, a 1st level over-current is detected. If four 1st level OC events are detected in four consecutive switching cycles, over-current protection will be triggered. 2nd level threshold: it is an internal threshold whose value is equal to 1st level threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this threshold, over-current protection will be triggered immediately.
When over-current protection is triggered, the device turns off both LS and HS MOSFETs in a latched condition. To recover from over-current protection triggered condition, VCC power supply must be cycled.
7.1
Over-current threshold setting
L6728A allows to easily program a 1st level over-current threshold ranging from 50 mV to 550 mV, simply by adding a resistor (ROCSET) between LGATE and GND. 2nd level threshold will be automatically set accordingly. During a short period of time (about 5 ms) following VCC rising over UVLO threshold, an internal 10 A current (IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as 1st level over-current threshold. The OC setting procedure overall time length is about 5 ms. Connecting a ROCSET resistor between LGATE and GND, the programmed 1st level threshold will be:
I OCSET R OCSET I OCth1 = ------------------------------------------R dsON
the programmed 2nd level threshold will be:
I OCSET R OCSET I OCth2 = 1.5 ------------------------------------------R dsON
In case ROCSET is not connected, the device sets the OCP thresholds to the maximum values: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches 600 mV, setting the maximum threshold and suddenly ending OC setting phase.
12/32
L6728A
Output voltage setting and protections
8
Output voltage setting and protections
L6728A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device comes with a fixed 0.8 V internal reference that guarantee the output regulated voltage to be within 1% tolerance over line and temperature variations (excluding output resistor divider tolerance, when present). Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB V OUT = V REF 1 + ---------- R OS
where VREF is 0.8 V. L6728A monitors the voltage at VSEN pin and compares it to internal reference voltage in order to provide under voltage and overvoltage protections as well as PGOOD signal. According to the level of VSEN, different actions are performed from the controller:
PGOOD If the voltage monitored through VSEN exits from the PGOOD window limits, the device de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is asserted at the end of the soft-start phase.
Under voltage protection If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and LS MOSFETs, latching the condition. Cycle VCC to recover.
Overvoltage protection If the voltage at VSEN pin rises over OV threshold (1 V typ), overvoltage protection turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as soon as VSEN goes below VREF/2 (0.4 V). The condition is latched, cycle VCC to recover. Notice that, even if the device is latched, the device still controls the LS MOSFET and can switch it on whenever VSEN rises above 0.4V.
Feedback disconnection protection In order to provide load protection even if VSEN pin is not connected, a 100 nA bias current is always sourced from this pin. If VSEN pin is not connected, this current will permanently pull it up causing the device to detect an OV: thus LS will be latched on preventing output voltage from rising out of control.
13/32
L6728A
Application details
9
9.1
Application details
Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is regulated to the internal reference (when present, offset resistor between FB node and GND can be neglected in control loop calculation). Error amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. The converter transfer function is the small signal transfer function between the output of the EA and VOUT. This function has a double pole at frequency FLC depending on the L-C output filter and a zero at FESR depending on the output capacitor ESR. The DC gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC. Figure 5. PWM control loop
VIN OSC V OSC
_ + PWM COMPARATOR ERROR AMPLIFIER + _
L
R COUT ESR
V OUT
VREF RFB
CF CP
RF
CS ZF
RS ZFB
The compensation network closes the loop joining VOUT and EA output with transfer function ideally equal to -ZF/ZFB. Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for stability, it should not exceed FSW/2. To achieve a good phase margin, the control loop gain has to cross 0 dB axis with -20 dB/decade slope. As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
14/32
L6728A Figure 6. Example of type III compensation
Gain [dB] open loop EA gain FZ1 FZ2 closed loop gain compensation gain open loop converter gain 0dB F0dB FLC FESR 20log (RF/RFB) FP1 FP2
Application details
20log (VIN/VOSC ) Log (Freq)
Open loop converter singularities: a) b)
1 F LC = --------------------------------2 L C OUT 1 F ESR = ------------------------------------------2 C OUT ESR
Compensation network singularities frequencies: a) b) c)
1 F Z1 = -----------------------------2 R F C F 1 F Z2 = ---------------------------------------------------2 ( R FB + R S ) C S 1 F P1 = ------------------------------------------------CF CP 2 R F -------------------- C F + C P 1 F P2 = -----------------------------2 R S C S
d)
To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB is in the range of some k):
F 0dB V OSC RF ---------- = ------------ -----------------F LC V IN R FB
15/32
L6728A
Application details
b)
Place FZ1 below FLC (typically 0.5*FLC):
1 C F = ---------------------------- R F F LC
c)
Place FP1 at FESR:
CF C P = ---------------------------------------------------------2 R F C F F ESR - 1
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
R FB R S = -------------------------F SW ----------------- - 1 2 F LC 1 C S = ----------------------------- R S F SW
e) f)
Check that compensation network gain is lower than open loop EA gain before F0dB; Check phase margin obtained (it should be greater than 45) and repeat if necessary.
9.2
Layout guidelines
L6728A provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 7) must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank.
16/32
L6728A Figure 7. Power connections (heavy lines)
VIN
Application details
UGATE PHASE
CIN L
L6728A
LGATE GND COUT LOAD
Gate traces and phase trace must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is recommended to minimize the distance between controller and power section. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and Bootstrap capacitor) and feedback compensation components as close to the device as practical. For over current programmability, place ROCSET close to the device and avoid leakage current paths on COMP/OC pin, since the internal current source is only 60 A. Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big negative spikes on the phase pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the boot capacitor (one resistor in series to BOOT). Figure 8.
LS DRIVER VCC CGD RGATE LGATE CGS CDS RINT UGATE CGS CDS RGATE RINT
Drivers turn-on and turn-off paths
LS MOSFET HS DRIVER BOOT CGD HS MOSFET
GND
PHASE
17/32
L6728A
Application information
10
10.1
Application information
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (IL) between 20% and 30% of the maximum output current (typ.). The inductance value can be calculated with the following relationship:
V IN - V OUT V OUT L = ----------------------------- -------------F SW I L V IN
where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from initial to final value. Until the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. If the compensation network is well designed, during a load variation the device is able to set a duty cycle value very different (0% or 80%) from steady state one. When this condition is reached, the response time is limited by the time required to change the inductor current.
18/32
L6728A
Application information
10.2
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During steady-state conditions, the output voltage ripple is influenced by both the ESR and capacitive value of the output capacitors as follow:
V OUT_ESR = I L ESR 1 V OUT_C = I L -------------------------------------8 C OUT F SW
Where IL is the inductor current ripple. In particular, the expression that defines VOUT_C takes in consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. During a load variation, the output capacitors supplies the current to the load or absorb the current stored into the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current slope is limited by the inductor value. The output voltage has a drop that also in this case depends on the ESR and capacitive charge/discharge as follow:
V OUT_ESR = I OUT ESR L I OUT V OUT_C = I OUT ------------------------------------2 C OUT V L
Where VL is the voltage applied to the inductor during the transient response ( D MAX VIN - VOUT for the load appliance or VOUT for the load removal). MLCC capacitors have typically low ESR to minimize the ripple but also have low capacitance that do not minimize the voltage deviation during dynamic load variations. On the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation during load transients while they does not show the same ESR values of the MLCC resulting then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC capacitor is suggested to minimize ripple as well as reducing voltage deviation in dynamic mode.
10.3
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current that depends on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as follow:
I rms = I OUT D ( 1 - D )
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depends on the input capacitor ESR and, in worst case, are:
P = ESR ( I OUT 2 )
2
19/32
L6728A
20 A demonstration board
11
20 A demonstration board
L6728A 20 A demonstration board realizes, in a two-layer PCB, a step-down DC/DC converter and shows the operation of the device in a general-purpose high-current application. Different output voltage rails have been considered: 8 V, 5 V, 3.3 V, 2.5 V, 1.25 V and 0.8 V. The input voltage can range from a bottom value that depends on the chosen rail up to 15 V buses (absolute maximum). The application can deliver an output current up to the value fixed by ROCSET (~27 A). Figure 9. 20 A demonstration board (left) and components placement (right)
Figure 10. 20 A demonstration board's top (left) and bottom (right) layers
20/32
L6728A Figure 11. 20 A demonstration board schematic
20 A demonstration board
21/32
L6728A Table 6.
Qty Capacitors 2 1 3 2 C1, C2 C10 C11 to C13 C14, C38 C3 to C9, C15 to C20, C39 to C59, C36, C37, C21 to C23, C25 to C29, C31 to C34 C30 C24 C35
20 A demonstration board 20A demonstration board - bill of material (common components)
Reference Description Package
Electrolytic capacitor 1800 F 16 V Sanyo P/N 16ME1800WG MLCC, 100 nF, 50 V, X7R Murata GRM188R71H104K MLCC, 4.7 F, 16 V, X7R Murata GRM31CR71C475K MLCC, 1 F, 16 V, X7R Murata GRM21BR71C105K Not mounted POSCAP 470 F, 6.3 V, 10 m Sanyo P/N 6TPD470M MLCC, 47 nF, 50 V, X7R Murata GRM188R71H473K
Radial 10 x 23 mm SMD0603 SMD1206 SMD0805
48
na
1 1 1
SMD1206
SMD0603 MLCC, 100 pF, 50 V, X7R Murata GRM188R71H101K
Resistors 4 5 5 1 1 Inductor Wurth SMD power inductor 670 nH - 1.75 m - 40 A P/N 744-315-067 Not mounted R1, R2, R20, R17 R3, R5, R11, R12, R16 R4, R10, R14, R15, R21 R19 R18 Resistor, 2R2, 1/16W, 1% Resistor, 0R, 1/8W, 1% Not mounted Resistor, 22 K, 1/16W, 1% SMD0603 Resistor, 18 K, 1/16W, 1% SMD0603 SMD0805 na
1 1
L1 L2
na
Active components 1 5 1 1 1 D1 Q1 to Q4, Q8 Q5 Q7 U1 Diode, 1N4148 Not mounted STD70NH02L DPACK STD95NH02L Controller, L6728A VFQFPN10, 3x3 mm SOT23 na
22/32
L6728A
20 A demonstration board
11.1
11.1.1
Demonstration board description
Power input (VIN)
This is the input voltage for the power conversion. The high-side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus. If the voltage is between 5 V and 12 V it can supply also the device (through the VCC pin) and in this case the R16 (0 ) resistor must be present.
11.1.2
Output (VOUT)
Different output voltage rails have been tested. For each rail a few component need to be changed: these components are used to program the desiderated output voltage and to compensate the system. The over-current-protection limit is set to ~27 A but it can be changed by replacing the resistors R18. Table 7.
Ref. Q9 R7 R6, R9 R8, R13
Rail dependent components
8 V rail 5 V rail 3.3 V rail 2.5 V rail 1.25 V rail 0.8 V rail
mounted 3.6 k 3.6 k 390 3.6 k 3.6 k 680 3.6 k 4.7 k 1.5 k
not mounted 3.6 k 4.7 k 2.2 k 11 k 22 k 39 k 11 k 22 k open
Note:
All the previous resistors are SMD 0603 package, 1/16W, 1% tolerance.
11.1.3
Signal input (VCC)
Using the input voltage VIN to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the VCC input and, in this case, the R16 (0 ) resistor must be unsoldered.
11.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing the device: - - - - - - - COMP: the output of the error amplifier; FB: the inverting input of the error amplifier; PGOOD: signaling the regular functioning (active high); VGDHS: the bootstrap diode anode; PHASE: Phase node; LGATE: Low-side gate pin of the device; HGATE: High-side gate pin of the device.
23/32
L6728A
20 A demonstration board
11.2
Demonstration board characterization
Figure 12 and Figure 17 show the electrical performances of the tamboured in terms of accuracy and efficiency. Figure 12. 20 A demonstration board performances
Load / Line Regulation 0,3% Output Voltage Error [%] 0,2% 0,1% 0,0% -0,1% -0,2% -0,3% 4 5 6 7 8 9 10 11 12 13 14 15 Input Voltage [V]
0A 5A 10A 15A 20A
Input Voltage @ 12 V 100% 90% Efficiency [%] 80% 70% 60% 50% 40% 0,0
Vout = 0.8 V Vout = 2.5 V Vout = 5 V Vout = 1.25 V Vout = 3.3 V Vout = 8 V
2,5
5,0
7,5
10,0
12,5
15,0
17,5
20,0
22,5
25,0
Output Current [A]
Input Voltage @ 8 V 100% 90% Efficiency [%] 80% 70% 60% 50% 40% 0,0
Vout = 0.8 V Vout = 2.5 V Vout = 5 V Vout = 1.25 V Vout = 3.3 V
Input Voltage @ 5 V 100% 90% Efficiency [%] 80% 70% 60% 50% 40%
Vout = 0.8 V Vout = 2.5 V Vout = 1.25 V Vout = 3.3 V
2,5
5,0
7,5
10,0
12,5
15,0
17,5
20,0
22,5
25,0
0
3
5
8
10
13
15
18
20
23
25
Output Current [A]
Output Current [A]
24/32
L6728A
5A demonstration board
12
5A demonstration board
L6728A 5 A demonstration board realizes, in a two-layer PCB, a step-down DC/DC converter and shows the operation of the device in a general-purpose high-current application. Different output voltage rails have been considered: 8 V, 5 V, 3.3 V, 2.5 V, 1.25 V and 0.8 V. The input voltage can range from a bottom value that depends on the chosen rail up to 15 V buses (absolute maximum). The application can deliver an output current up to the value fixed by ROCSET (~6 A). Figure 13. 5 A demonstration board (left) and components placement (right)
Figure 14. 5 A demonstration board's top (left) and bottom (right) layers
25/32
L6728A Figure 15. 5 A demonstration board schematic
5A demonstration board
26/32
L6728A Table 8.
Qty Capacitors 2 1 2 2 2 1 1 Resistors 3 3 1 2 2 1 1 1 Inductor Wurth SMD power inductor 1.8 H - 3.68 m - 20 A P/N 744-318-180 R1, R2, R17 R3, R5, R16 R14 R6, R9 R8, R13 R7 R19 R18 Resistor, 3R3, 1/16 W, 1% Resistor, 0R, 1/8 W, 1% Resistor, 51R, 1/8 W, 1% Resistor, 2K2, 1/16 W, 1% C12, C51 C10 C14, C38 C39, C40 C36 C24 C35 MLCC, 10 F, 16 V, X5R Murata GRM31CR61C106K MLCC, 100 nF, 50 V, X7R Murata GRM188R71H104K MLCC, 1 F, 16 V, X7R Murata GRM21BR71C105K MLCC, 22 F, 6.3 V, X5R Murata GRM31CR60J226K MLCC, 10 nF, 50 V, X7R Murata GRM188R71H103K MLCC, 47 nF, 50 V, X7R Murata GRM188R71H223K MLCC, 1 nF, 50 V, X7R Murata GRM188R71H102K
5A demonstration board 5 A demonstration board - bill of material
Reference Description Package
SMD1206 SMD0603 SMD0805 SMD1206
SMD0603
SMD0603 Resistor, 3K9, 1/16 W, 1% Resistor, 270 R, 1/16 W, 1% Resistor, 22 K, 1/16 W, 1% Resistor, 18 K, 1/16 W, 1%
1
L1
na
Active Components 1 1 D1 Q5 Diode, BAT54 Dual N-channel MOS, STS8DNF3LL (the STS8DNH3LL model can be used as well) Controller, L6728A SOT23 SO8 VFQFPN 10 3x3 mm
1
U1
27/32
L6728A
5A demonstration board
12.1
12.1.1
Demonstration board description
Power input (VIN)
This is the input voltage for the power conversion. The High-Side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus. If the voltage is between 5 V and 12 V it can supply also the device (through the Vcc pin) and in this case the R16 (0 ) resistor must be present.
12.1.2
Output (VOUT)
Different output voltage rails have been tested. For each rail a few component need to be changed: these components are used to program the desiderate output voltage. The OCP limit is set to ~6 A but it can be changed by replacing the resistors R18. Table 9.
Ref. R8, R13
Rail dependent components
8 V rail 240 5 V rail 430 3.3 V rail 680 2.5 V rail 1 k 1.25 V rail 3.9 k 0.8 V rail open
Note:
All the previous resistors are SMD 0603 package, 1/16W, 1% tolerance.
12.1.3
Signal input (VCC)
Using the input voltage VIN to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the VCC input (5-12 V) and, in this case, the R16 (0 ) resistor must be unsoldered.
12.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing the device: - - - - - - - COMP: the output of the error amplifier; FB: the inverting input of the error amplifier; PGOOD: signaling the regular functioning (active high); VGDHS: the bootstrap diode anode; PHASE: Phase node; LGATE: Low-Side gate pin of the device; HGATE: High-Side gate pin of the device.
28/32
L6728A
5A demonstration board
12.2
Demonstration board characterization
Figure 16 and Figure 17 show the electrical performances of the demonstration board in terms of accuracy and efficiency. Figure 16. 5 A demonstration board performances
Load / Line Regulation 0,3% Output Voltage Error [%] 0,2% 0,1% 0,0% -0,1% -0,2% -0,3% 4 5 6 7 8 9 10 11 12 13 14 15 Input Voltage [V] Input Voltage @ 8 V 100% 90% Efficiency [%]
Efficiency [%] 100% 90% 80% 70% 60% 50% 40% Vout = 0.8 V Vout = 2.5 V Vout = 1.25 V Vout = 3.3 V 4,0 4,5 5,0 5,5
0A 2.5A 5A
Input Voltage @ 12 V 100% 90% Efficiency [%] 80% 70% 60% 50% 40% 0,0
Vout = 0.8 V Vout = 2.5 V Vout = 5 V Vout = 1.25 V Vout = 3.3 V Vout = 8 V
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5,5
Output Current [A]
Input Voltage @ 5 V
80% 70% 60% 50% 40% 0,0
Vout = 0.8 V Vout = 2.5 V Vout = 5 V Vout = 1.25 V Vout = 3.3 V
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5,5
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
Output Current [A]
Output Current [A]
Figure 17. Demonstration boards power consumption @ 0 A output current
5A Demoboard Power Consumption 1,2 1,0 Power [W]
Power [W] 1,2 1,0 0,8 0,6 0,4 0,2 0,0 20A Demoboard Power Consumption
0,8 0,6 0,4 0,2 0,0 4 5 6 7 8 9 10 11 12 13 14 15 Input Voltage [V]
4
5
6
7
8
9
10
11
12
13
14
15
Input Voltage [V]
29/32
L6728A
Mechanical data and package dimensions
13
Mechanical data and package dimensions
Figure 18. Mechanical data and package dimensions
DIMENSIONS REF.
A A1 A2 A3 b D D2 E E2 e L
M m
mm MIN. TYP. MAX. MIN.
0.80 0.90 0.02 0.70 0.20 0.18 0.23 3.00 2.21 2.26 3.00 1.49 1.64 0.50 0.3 0.4
0.75 0.25
mils TYP.
35.43 0.787 27.55 7.874 0.30 7.086 9.055 118.1 2.31 87.00 88.97 118.1 1.74 58.66 64.56 19.68 0.5 11.81 15.74
29.52 9.842
MAX.
39.37 1.968
PACKAGE AND PACKING INFORMATION
1.00 0.05
31.49
Very thin Fine pitch Dual Flat Packages No lead
11.81 Weight: not available
90.94
68.50
19.68
VFDFPN10 3x3mm
m
M
30/32
L6728A
Revision history
14
Revision history
Table 10. Document revision history
Date 01-Oct-2008 Revision 1 Initial release Changes
31/32
L6728A
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
32/32

▲Up To Search▲

Price & Availability of L6728ATR

	To Download L6728ATR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .